The present invention relates to a clock supply circuit suitable for use in a semiconductor integrated circuit. More specifically, the present invention relates to a clock supply circuit suitable for use in a semicustom LSI which enables the design of a circuit based on conductors or conductive patterns determined by a user, particularly a full-face element spread-type (sea of gates type) LSI.
In clock supply circuits for supplying clock pulses to logic circuits activated in response to the clock pulses, there occurs a time difference, i.e., variations in time delays in the respective clock pulses input to the corresponding logic circuits. This results from the fact that conductive patterns between the clock supply circuits and their corresponding logic circuits are different in length from one another.
There have therefore been proposed a method disclosed in Japanese Patent Application Laid-Open Publication No. 1-157115 and a method disclosed in VLD89-103 entitled "0.8 .mu.m CMOSSOG with High-Performance Clock Distributing Function" by Institute of Electronic Information and Communication and Society for Research of VLSI Design and Technology. In the former disclosure, an area where logic circuits exist are divided into a plurality of regions each of which has a clock pulse supply circuit disposed centrally therein in such a manner that conductive patterns between the clock pulse supply circuit and the individual logic circuits are equal in length to each other. In the latter disclosure as well, clock supply circuits are disposed in both ends of respective areas where logic circuits exist. A main conductive pattern is provided so as to be electrically connected with both ends of the respective areas. A clock pulse is supplied from the main conductive pattern to the respective logic circuits via branch conductive patterns.
However, each of the clock supply circuits has been positioned as described above. It is therefore necessary to provide regions dedicated to the clock supply circuits. Further, the clock supply circuits cannot be also disposed flexibly depending on the positions where the logic circuits exist.